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1 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 description integrated synthesizer plus fanout buffers, clock dividers, and translator in a single 64-pin package accepts any reference input between 14mhz to 160mhz (single-ended or differential) 33mhz to 500mhz output frequency range lvpecl and hstl outputs 3.3v 10% power supply low jitter: <50ps cycle-to-cycle low pin-to-pin skew: <50ps ttl/cmos compatible control logic 3 independently programmable output frequency banks: 9 differential output pairs @bankb (hstl) 2 differential output pairs @banka (lvpecl) 2 differential output pairs @bankc (lvpecl) available in 64-pin epad-tqfp features 3.3v, precision, 33mhz to 500mhz programmable lvpecl and hstl bus clock synthesizer precision edge sy89536l applications servers workstations parallel processor-based systems other high-performance computing communications rev.: d amendment: /0 issue date: january 2008 the sy89536l programmable clock synthesizer is part of a 3.3v, high-frequency, precision pll-based clock synthesizer family optimized for multi-frequency, large clock- tree applications. this device integrates the following blocks into a single monolithic ic: pll (phase-lock-loop)-based synthesizer fanout buffer clock generator (divider) logic translation (lvpecl, hstl) the sy89536l includes a flexible input design that accepts any reference input; single-ended lvttl/cmos, sstl and differential lvpecl, lvds, hstl, and cml. this level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. for applications that must interface to a crystal oscillator, see the sy89531l. data sheets and support documentation can be found on micrel? web site at www.micrel.com. product selection guide input output device crystal r eference banka bankb bankc sy89531l* x lvpecl hstl lvpecl sy89532l* x lvpecl lvpecl lvpecl sy89533l* x lvpecl lvds lvpecl sy89534l* x lvpecl lvpecl lvpecl sy89535l* x lvpecl lvds lvpecl sy89536l x lvpecl hstl lvpecl *refer to individual data sheet for details. precision edge is a registered trademark of micrel, inc. precision edge
2 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 package/ordering information vcc_logic qb0 vccob /qa1 qa1 /qa0 qa0 vccoa fsel_a2 fsel_a1 fsel_a0 out_sync vcc_logic vcca gnd nc* nc* nc* nc* gnd psel1 psel0 loop_ref loop_filter gnd refclk /refclk vbb_ref m(3) m(2) m(1) m(0) /qb0 qb1 /qb1 qb2 /qb2 qb3 /qb3 qb4 /qb4 qb5 /qb5 qb6 /qb6 qb7 /qb7 qb8 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 qc0 /qb8 vccob vccob gnd fsel_b0 fsel_b1 fsel_b2 gnd fsel_c0 fsel_c1 fsel_c2 vccoc /qc0 qc1 /qc1 64-pin epad-tqfp (h64-1) *nc: do not connect, leave floating. ordering information (1) package operating package lead part number type range marking finish sy89536lhc h64-1 commercial sy89536lhc sn-pb sy89536lhctr (2) h64-1 commercial sy89536lhc sn-pb sy89536lhz (3) h64-1 commercial sy89536lhz with pb-free pb-free bar-line indicator matte-sn SY89536LHZTR (2, 3) h64-1 commercial sy89536lhz with pb-free pb-free bar-line indicator matte-sn notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 pin description power pin number pin name pin function 60, 61 v cc_logic power for core logic: connect to 3.3v supply. 3.3v power pins are not internally connected on the die, and must be connected together on the pcb. 62 v cca power for pll: connect to quiet 3.3v supply. 3.3v power pins are not internally connected on the die, and must be connected together on the pcb. 55 v cco a power for output drivers: connect v cco a and v cco c pins to 3.3v supply and v cco b 30, 31, 50 v cco b pins to 1.8v supply. 21 v cco c 4, 9, 25, 63, 29 gnd ground: all gnd pins must be tied together on the pcb. exposed pad must be (exposed pad) soldered to a ground plane. configuration pin number pin name pin function 4 vco_sel lvttl/cmos compatible input: selects between internal or external vco. when tied low (gnd) internal vco is selected. for external vco, leave floating (default condition is logic high). internal 25k ? pull-up. 5, 6 psel(1:0) lvttl/cmos compatible input: controls input frequency pre divider. internal 25k ? pull-up. default is logic high. see pre-divide frequency select table. 7 loop ref analog input/output: provides the reference voltage for pll loop filter. 8 loop filter analog input/output: provides the loop filter for pll. see external loop filter considerations for loop filter values. 13,14,15,16 m (3:0) lvttl/cmos compatible input: used to change the pll feedback divider. internal 25k ? pull-up. m0 = lsb. default is logic high. see feedback divide select table. 22, 23, 24 fsel_c (2:0) lvttl/cmos compatible input: bank c post-divide select. internal 25k ? pull-up. default is logic high. see post-divide frequency select table. fsel_c0 = lsb. 26, 27, 28 fsel_b (2:0) lvttl/cmos compatible input: bank b post-divide select. internal 25k ? pull-up. default is logic high. see post-divide frequency select table. fsel_b0 = lsb. 56, 57, 58 fsel_a (2:0) lvttl/cmos compatible input: bank a post-divide select. internal 25k ? pull-up. default is logic high. see post-divide frequency select table. fsel_a0 = lsb. 59 out_sync banks a, b, c output synchronous control: (lvttl/cmos compatible). internal 25k ? pull-up. after any bank has been programmed, toggle with a high-low-high pulse to resynchronize all output banks. input/output pin number pin name pin function 1, 2, 3 nc no connect: leave floating. 10, 11 refclk, reference input: this flexible input accepts any input ttl/cmos, lvpecl, lvds, /refclk hstl, sstl logic levels. see input interface section. 12 vbb_ref reference output voltage. used for single-ended input. maximum sink/source current = 0.5ma. 51, 52, 53, 54 qa1 to qa0 bank a 100k lvpecl output drivers: output frequency is controlled by fsel_a (0:2). terminate outputs with 50 ? to v cc 2v. see output termination recommendations section. 32 49 qb8 to qb0 bank b output drivers: differential hstl outputs. see output termination recommendations section. output frequency is controlled by fsel_b (0:2). 17, 18, 19, 20 qc1 to qc0 bank c 100k lvpecl output drivers: output frequency is controlled by fsel_c (0:2). terminate outputs with 50 ? to v cc 2v. see output termination recommendations section. 64 nc no connect: leave floating.
4 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (note 1) supply voltage (v in ) ................................... 0.5v to +4.0v v cc pin potential to ground pin (all v cc ).. 0.5v to +4.0v input voltage (v in ) ........................................ 0.5v to v cci dc output current (i out ) lvpecl, hstl outputs ....................................... 50ma lead temperature (soldering, 20 sec.) ..................... 260 c storage temperature (t s ) ....................... 65 c to +150 c operating ratings (note 2) supply voltage v cco a and v cco c .................................... 3.0v to +3.6v v cco b ....................................................... 1.6v to +2.0v ambient temperature (t a ) ............................. 0 c to +85 c package thermal resistance (junction-to-ambient) with die attach soldered to gnd: tqfp ( ja ) still-air .............................................. 23 c/w tqfp ( ja ) 200lfpm ............................................ 18 c/w tqfp ( ja ) 500lfpm ............................................ 15 c/w with die attach not soldered to gnd, note 3 : tqfp ( ja ) still-air .............................................. 44 c/w tqfp ( ja ) 200lfpm ............................................ 36 c/w tqfp ( ja ) 500lfpm ............................................ 30 c/w package thermal resistance (junction-to-case) tqfp ( jc ) ......................................................... 4.0 c/w power supply symbol parameter condition min typ max units v cca pll and logic supply voltage note 4 3.0 3.3 3.6 v v cc_logic v cco a/c bank a and c v cc output 3.0 3.3 3.6 v v cco b bank b v cc output lvpecl/hstl 1.6 1.8 2.0 v i cc total supply current note 5 230 295 ma dc electrical characteristics note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng con ditions for extended periods may affect device reliability. note 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. it is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. note 4. v cca , v cc_logic , v cco a/c are not internally connected together inside the device. they must be connected together on the pcb. v cco b is a separate supply. note 5. no load. outputs floating, banks a, b, and c enabled.
5 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 dc electrical characteristics lvcmos/lvttl input control logic (v cca , v cc_logic , v cco a/c pins = +3.3v 10%) symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current 150 a i il input low current 300 a refclk (pins 10, 11) input (all v cc pins except v cco b = +3.3v 10%, v cco b = +1.8v 10%) symbol parameter condition min typ max units v id differential input voltage 100 mv v ih input high voltage v cc +0.3 v v il input low voltage 0.3 v 100k lvpecl outputs (all v cc pins except v cco b = +3.3v 10%, v cco b = +1.8v 10%) symbol parameter condition min typ max units v oh output high voltage note 6 v cc 1.145 v cc 1.020 v cc 0.895 v v ol output low voltage note 6 v cc 1.945 v cc 1.820 v cc 1.695 v v id differential input voltage note 7 100 mv 200 mv v ih input high voltage note 7 v cc +0.3 v v il input low voltage note 7 0.3 v i ih input high current 600 300 a i il input low current 1200 700 a v bb output reference voltage v cc 1.325 v cc 1.425 v cc 1.525 v hstl outputs (bank b qb0:8) (all v cc pins except v cco b = +3.3v 10%, v cco b = +1.8v 10%) (note 8) symbol parameter condition min typ max units v out output voltage swing 800 mv v oh output high voltage 1.0 1.2 v v ol output low voltage 0.2 0.4 v note 6. 50 ? to v cc 2v. banks a, b, and c enabled. note 7. v cc = 3.0v to 3.6v.
6 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 v cc_logic = v cc a/c = +3.3v 10%, v cco b = +1.8v 10% symbol parameter condition min typ max units f in reference input frequency 14 160 mhz f out output frequency range 33.33 500 mhz t vco internal vco frequency range 600 1000 mhz t skew within device skew within bank pecl note 9 50 ps within bank hstl note 9 75 ps bank-to-bank note 9 60 150 ps part-to-part skew note 10 200 ps t lock maximum pll lock time 10 ms t jitter cycle-to-cycle jitter (pk-to-pk) note 11 50 ps period jitter (rms) note 12 50 ps t pw (min) minimum pulse width 50 ps target pll loop bandwidth feedback divider ratio: 66 note 13 1.0 mhz feedback divider ratio: 30 note 13 2.0 mhz t dc f out duty cycle 45 50 55 % t r , t f output rise/fall time (20% to 80%) lvpecl_out 250 400 ps hstl_out 100 400 ps t output_reset note 14 10 ns t hold_fsel note 14 5 ns t setup_fsel note 14 5 ns t output_sync note 14 1 vco clock cycle fsel-to-valid output transition time 50 ns t setup_out_sync 500 ps note 8. all hstl outputs loaded with 50 ? to gnd. note 9. the within-device skew is defined as the worst case difference between any two similar delay paths within a single devic e operating at the same voltage and temperature. note 10. the part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices o perating at the same voltage and temperature. note 11. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycl e pairs. t jitter_cc =t n t n+1 where t is the time between rising edges of the output signal. note 12. period jitter definition: for a specified amount of time (i.e., 1ms), there are n periods of a signal, and t n is defined as the average period of that signal. period jitter is defined as the variation in the period of the output signal for corresponding edges relative to t n . note 13. using recommended loop filter components. note 14. see timing diagrams." ac electrical characteristics
7 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 timing diagrams conditions: internal vco, unless otherwise stated. t hold_fsel vco fsel fout out_sync t output_sync 010 time 001 t setup_fsel t output_reset frequency programming vco (ext.) fsel fout out_sync t output_sync 010 time 001 t setup_ out_sync t output_reset frequency programming (external vco clock) vco fsel fout out_sync 010 time 001 f sel to valid output transition time output frequency updates to valid output
8 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 functional block diagram pre divider 1, 2, 4, 8 4 5 6 7 8 v cc 1.425v reference or bandgap reference charge pump phase detector 12 13 14 62 61 64 63 23 1 60 58 57 56 54 53 52 51 3-bit divider a 2, 4, 6, 8, 10, 12,18 psel0 vco_sel pesl1 loopref loopfilter vbb_ref (msb) m3 3 2x 9x 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 29 28 27 26 25 24 23 22 21 20 19 18 3 vco (600mhz to 1000mhz) 14mhz to 20mhz 14mhz to 20mhz /qa1 v cco b qb0 /qb0 qb1 /qb1 qb2 /qb2 qb3 /qb3 qb4 /qb4 qb5 /qb5 qb6 /qb6 qb7 /qb7 qb8 /qb8 59 31 30 v cco b v cco b qa1 /qa0 qa0 55 v cco a a en b en 3-bit divider b 2, 4, 6, 8, 10, 12, 18 3-bit divider c 2, 4, 6, 8, 10, 12, 18 c en fsel_a2 fsel_a1 fsel_a0 (lsb) out_sync m-divide 30, 32, 34, 36, 38, 40, 42, 44, 48, 50, 52, 54, 56, 60, 62, 66 v cc _logic v cc _logic v cc a gnd nc nc nc nc 9 gnd 10 refclk 11 /refclk mux 1 clock gnd fsel_b0 (lsb) fsel_b1 fsel_b2 gnd fsel_c0 (lsb) fsel_c1 fsel_c2 17 v cco c qc0 /qc0 qc1 /qc1 3 buf 5 4 0 = use internal pll 1 = bypass internal pll (default) 600mhz to 1000mhz 2x m2 15 16 m1 (lsb) m0
9 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 functional description at the core of the sy89536l clock synthesizer is a precision pll driven by a differential or single-ended reference input. for users who wish to supply a crystal input, please use the sy89531l. the pll output is sent to three banks of outputs. each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. pll programming and operation important: if the internal vco will be used, vco_sel must be tied low, and extvco pins can be left unconnected. the internal vco range is 600mhz to 1000mhz, and the feedback ratio is selectable via the msel divider control (m3:0 pins). the feedback ratio can be changed without powering the chip down. the pll output is fed to three banks of outputs: bank a, bank b, and bank c. banks a and c each have two differential lvpecl output pairs. bank b has nine differential hstl output pairs. each bank has a separate frequency divider circuit that can be reprogrammed on the fly. the fsel_x0:2 (where x is a, b, or c) pins control the divider value. the fsel divider can be programmed in ratios from 2 to 18, and the outputs of banks a, b, and c can be synchronized after programming by pulsing the out_sync pin high-low- high. setting a value of 000 for fsel is an output disable forcing the q outputs to be low and the /q outputs to be high. doing so will decrease power consumption by approximately 5ma per bank. to determine the correct settings for sy89536l follow these steps: 1. refer to the suggested selections for specific customer applications section for common applications, as well as the formula used to compute the output frequency. 2. determine the desired output frequency, such as 66mhz. 3. choose a reference input frequency between 14mhz and 20mhz. the user can also choose a higher input frequency, and use the psel pre-divider to divide it down to the 14mhz to 20mhz range. in this example, we choose 18mhz for the reference input frequency. this results in an input/output ratio of 66/18. 4. refer to the feedback divide select table and the post-divide frequency select table to find values for msel and fsel such that msel/fsel equals the same 66/18 ratio. in this example, values of msel=44 and fsel=12 work. 5. make sure that refclk psel msel is between 600mhz and 1000mhz. the user may need to experiment with different refclk input frequencies to satisfy these requirements. 470pf loop filter loop reference 330 ? 0.2 f figure 1. external loop filter connection external loop filter considerations the sy89536l features an external pll loop filter that allows the user to tailor the pll s behavior to their application and operating environment. we recommend using ceramic capacitors with npo or x7r dielectric, as they have very low effective series resistance. for applications that require ultra-low cycle-to-cycle jitter, use the components shown in figure 1. the pll loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. for instance, the pll s loop bandwidth can be decreased by using a smaller resistor in the loop filter. this results in less noise from the pll input, but potentially more noise from the vco. refer to ac electrical characteristics for target pll loop bandwidth. the designer should take care to keep the loop filter components on the same side of the board and as close as possible to the sy89536l s loop_ref and loop_filter pins. to insure minimal noise pick-up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. however, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces. power supply filtering techniques as with any high-speed integrated circuit, power supply filtering is very important. at a minimum, v cc a, v cc _logic, and all v cco pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. to achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in figure 2.
10 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 *for v cc_ analog,v cc_ttl, v cc1, use ferrite bead = 200ma, 0.45 ? dc, murata p/n blm21a1025 *for v cco a,b,c use ferrite bead = 3a, 0.025 ? dc, murata, p/n blm31p005 *component size: 0805 1 f 22 f 0.01 f ferrite bead* power supply side device side v cc pins figure 2. power supply filtering output logic characteristics see output termination recommendations for illustrations. in cases where single-ended output is desired, the designer should terminate the unused complimentary output in the same manner as the normal output that is being used. unused output pairs can be left floating. lvpecl operation: typical voltage swing is 700mv pp to 800mv pp into 50 ? . common mode voltage is v cc 1.3v, typical. 100 ? termination across the output pair is not recommended for lvpecl. see output termination section, figures 5 to 7. hstl operation (bank b): typical voltage swing is 250mv pp to 450mv pp into effective 50 ? . thermal considerations this part has an exposed die pad for enhanced heat dissipation. we strongly recommend soldering the exposed die pad to a ground plane. where this is not possible, we recommend maintaining at least 500lfpm air flow around the part. for additional information on exposed-pad characteristics and implementation details, see amkor technology s web site, www.amkor.com. refclk input interface the flexible refclk inputs are designed to accept any differential or single-ended input signal within 300mv above v cc and 300mv below ground. do not leave unused refclk inputs floating. tie either the true or complement inputs to ground, but not both. a logic zero is achieved by connecting the complement input to ground with the true input floating. for a ttl input, tie a resistor between the complement input and ground. see input interface section, figures 4a through 4h. input levels lvds, cml and hstl differential signals may be connected directly to the refclk inputs. depending on the actual worst case voltage seen, the minimum input voltage swing varies. r2 990 ? r2 990 ? r1 825 ? r1 825 ? gnd refclk v cc /refclk figure 3. simplified input structure
11 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 psel1 (msb) psel0 reference input frequency 0 0 refclk 8 0 1 refclk 4 1 0 refclk 2 1 1 refclk 1 pre-divide frequency select table (psel) fsel_a2 (1) (msb) fsel_a1 (1) fsel_a0 (1) (lsb) output divider 0 0 0 output disable function, all outputs: q = low, /q = high 0 0 1 vco 2 0 1 0 vco 4 0 1 1 vco 6 1 0 0 vco 8 1 0 1 vco 10 1 1 0 vco 12 1 1 1 vco 18 note 1. same dividers apply to fsel_b (0:2) and fsel_c (0:2). post-divide frequency select table (fsel)
12 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 rate fsel msel refclk protocol (mhz) (post divider) (feedback div.) (mhz) psel fout pci 33 18 36 16.67 1 33 fast ethernet 100 6 40 15 1 100 1/8 fc 133 6 52 15.36 1 133 escon 200 4 50 16 1 200 suggested selections for specific customer applications (notes 1, 2, 3) note 1. 600mhz < (refclk psel msel) < 1000mhz. note 2. 14mhz (refclk psel) 20mhz. note 3. where two settings provide the user with the identical desired frequency, the setting with the higher pll input referenc e frequency (and lower feedback divider) will usually have lower output jitter. however, the reference input frequency, as well as the vco frequency, must be kept within their respective ranges. fout refclk psel msel fsel = ? () m3 m2 m1 m0 vco frequency (1) 0000 refclk psel 34 0001 refclk psel 36 0010 refclk psel 38 0011 refclk psel 40 0100 refclk psel 42 0101 refclk psel 44 0110 refclk psel 48 0111 refclk psel 50 1000 refclk psel 52 1001 refclk psel 54 1010 refclk psel 56 1011 refclk psel 60 1100 refclk psel 62 1101 refclk psel 66 1110 refclk psel 30 1111 refclk psel 32 feedback divide select table (msel)
13 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 input interface refclk /refclk sy89536l ttl lvttl 1% v cc(driver) v cc v cc(driver) figure 4a. 3.3v ttl cml refclk /refclk v cc(driver) v cc v cc(driver) 102 ? 1% sy89536l figure 4b. cml dc-coupled refclk /refclk sy89536l 2.5v lvttl 1% 2.3v to 2.7v 3.0v to 3.6v figure 4c. 2.5v lvttl refclk /refclk 50 ? 1% 50 ? 1% v cc(driver) v cc v cc(driver) sy89536l v cc 2v pecl figure 4d. 3.3v lvpecl dc-coupled hstl refclk /refclk sy89536l v cc 50 ? 50 ? figure 4e. hstl refclk /refclk 3.92k ? 1% 3.92k ? 1% 102 ? 1% v cc(driver) v cc sy89536l cml figure 4f. cml ac-coupled (short trace lengths)
14 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 cml refclk /refclk 130 ? 1% 130 ? 1% v cc(driver) v cc sy89536l 82 ? 1% 82 ? 1% v cc figure 4g. cml ac-coupled (long trace lengths) lvds refclk /refclk v cc 100 ? 1% sy89536l figure 4h. lvds
15 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 output termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v source destination figure 5. pecl parallel termination thevenin equivalent (note 1) z o = 50 ? z o = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v source destination r b c1 (optional) 0.01 f figure 6. pecl three-resistor y-termination (notes 1, 2, 3) z o = 50 ? z o = 50 ? +3.3v +3.3v source destination 50 ? 50 ? figure 7. hstl differential termination (note 1) note 1. place termination resistors as close to destination inputs as possible. note 2. pecl y-termination is a power-saving alternative to thevenin termination. note 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? .
16 precision edge sy89536l micrel, inc. m9999-010808 hbwhelp@micrel.com or (408) 955-1690 64-pin epad-tqfp (die up) (h64-1) rev. 02 +0.05 0.05 +0.002 0.002 +0.006 0.006 +0.012 0.012 +0.002 0.002 +0.15 0.15 +0.03 0.03 +0.05 0.05 +0.012 0.012 +0.05 0.05 package ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 64-pin epad-tqfp package package notes: note 1. package meets level 2 moisture sensitivity classification, and is shipped in dry-pack form. note 2. exposed pads must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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